Altera Cyclone V Device Handbook page 790

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2013.12.30
Table 15-1: ARM JTAG-AP Signal Use in the Scan Manager
The following table describes how the ARM JTAG-AP signals are connected in the scan manager. These signals are
internal to the scan manager, are provided here for reference only, and are not shown in the preceding figure. The
signal, register, and field names listed in the table match the names used in the ARM Debug Interface v5 Architecture
Specification.
Signal
SRSTCONNECTED[7:0]
PORTCONNECTED[7:0]
PORTENABLED[7:0]
nSRSTOUT[7:0]
nTRST*[7:0]
Scan Manager
Send Feedback
Scan Manager Block Diagram and System Integration
Direction
Input
Input
Input
Output
Output
Implementation
Tied to 0. The read-only
SRSTCONNECTED field in the
CSW register always reads as 0.
Tied to 0x8F, which connects only
ports 0-3 and 7. The read-only
PORTCONNECTED field in the
CSW register reads as 1 when the
PORTSEL register is written with
a value that enables one of the
connected ports, and reads as 0,
otherwise.
Tied to 0x8F, so all connected
ports are always considered
powered on. The PSTA register
does not contain a useful value, so
there is no reason for software to
access it. Software does not need
to monitor the status of ports 0-3
because they are always on. For
port 7, software can read the
mode field of the stat register
in the FPGA manager to
determine the FPGA power status.
Not connected. Writing to the
SRST_OUT field of the CSW
register has no effect.
nTRST*[7] is connected to the
FPGA JTAG TAP controller and
nTRST*[6:0] are not
connected. Writing to the TRST_
OUT field of the CSW register (the
trst bit of the stat register in
the scan manager) has an effect
only when port 7 is enabled by
software. For details, refer to
Communicating with the JTAG
TAP Controller section.
Altera Corporation
15-3