Pipe Reverse Parallel Loopback; Reverse Serial Loopback - Altera Cyclone V Device Handbook

CV-53006
2013.05.06
Related Information
Altera Transceiver PHY IP Core User Guide

PIPE Reverse Parallel Loopback

This section describes PIPE Reverse Parallel Loopback debugging option using parallel data through the
rate match FIFO, transmitter serializer, and tx_serial_data port path.
PIPE reverse parallel loopback is only available in the PCIe
Figure 2 shows the received serial data passing through the receiver CDR, deserializer, word aligner, and
rate match FIFO buffer. The parallel data from the rate match FIFO is then looped back to the transmitter
serializer and transmitted out through the tx_serial_data port. The received data is also available to
the FPGA fabric through the rx_parallel_data signal.
PIPE reverse parallel loopback is compliant with the PCIe 2.0 specification. To enable this loopback
configuration, assert the tx_detectrx_loopback signal.
Note: PIPE reverse parallel loopback is the only loopback option supported in the PCIe configuration.
Figure 6-3: PIPE Reverse Parallel Loopback Configuration Datapath
Transmitter PMA
Receiver PMA
Note: Grayed-out blocks are not active when the PIPE reverse parallel loopback is enabled.

Reverse Serial Loopback

You can use the reverse serial loopback option to debug with data through the rx_serial_data port,
receiver CDR, and tx_serial_data port path.
You can enable reverse serial loopback through the reconfiguration controller.
Note: For further details, refer to the Altera Transceiver PHY IP Core User Guide.
In reverse serial loopback, the data is received through the rx_serial_data port, re-timed through the
receiver CDR, and sent to the tx_serial_data port. The received data is also available to the FPGA
logic. No dynamic pin control is available to select or deselect reverse serial loopback.
The transmitter buffer is the only active block in the transmitter channel. You can change the V
pre-emphasis first post tap values on the transmitter buffer through the dynamic reconfiguration controller.
Transceiver Loopback Support
Send Feedback
Transmitter PCS
Reverse Parallel Loopback Path
Receiver PCS
PIPE Reverse Parallel Loopback
®
configuration for Gen1 and Gen2 data rates.
6-3
FPGA
Fabric
and the
OD
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