Interface Peripherals - Altera Cyclone V Device Handbook

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Watchdog Timers
Watchdog Timers
The two watchdog timers are based on the Synopsys DesignWare APB Watchdog Timer peripheral and
offer the following features:
• 32-bit timer resolution
• Interrupt request
• Reset request
• Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock
frequency)
Related Information
Watchdog Timer
DMA Controller
The DMA controller provides high-bandwidth data transfers for modules without integrated DMA controllers.
The DMA controller is based on the ARM Corelink
features:
• Microcoded to support flexible transfer types
• Supports up to eight channels
• Supports flow control with 31 peripherals handshake interfaces
Related Information
DMA Controller
FPGA Manager
The FPGA manager offers the following features:
• Manages configuration of the FPGA portion of the device
• 32-bit fast passive parallel configuration interface to the FPGA CSS block
• Partial reconfiguration
• Compressed FPGA configuration images
• Advanced Encryption Standard (AES) encrypted FPGA configuration images
• Monitors configuration-related signals in FPGA
• Provides 32 general-purpose inputs and 32 general-purpose outputs to the FPGA fabric
Related Information
FPGA Manager

Interface Peripherals

EMACs
The two EMACs are based on the Synopsys DesignWare 3504-0 Universal 10/100/1000 Ethernet MAC and
offer the following features:
• Supports 10, 100, and 1000 Mbps standard
• Supports RGMII external PHY interface
• Integrated DMA controller
Altera Corporation
on page 24-1
on page 16-1
on page 13-1
™
DMA Controller (DMA-330) and offers the following
Introduction to Cyclone V Hard Processor System (HPS)
cv_54001
2013.12.30
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