Transceiver Banks - Altera Cyclone V Device Handbook

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Cyclone V Device Handbook: Known Issues

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Transceiver Banks

Cyclone V transceivers are grouped in transceiver banks of three channels. Some Cyclone V devices support

four or five transceiver channels.

Every transceiver bank is comprised of three channels (ch 0, ch 1, and ch 2, or ch 3, ch 4 , and ch 5). The

Cyclone V device family has a total of four transceiver banks (for the largest density family) namely, GXB_L0,

GXB_L1, GXB_L2 and GXB_L3.

The location of the transceiver bank boundaries are important for clocking resources, bonding channels,

and fitting.

In some package variations, the total transceiver count is reduced.

Figure 1-2: GX/GT Devices with Three or Five Transceiver Channels and One PCIe HIP Block

The PCIe HIP block is located across Ch 1 and Ch 2 of banks GXB_L0.

Transceiver Architecture in Cyclone V Devices

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1. 3-channel device transceiver channels are located on bank L0.

2. 5-channel device transceiver channels are located on bank L0,

and Ch 3 and Ch 4 of bank L1.

PCIe Hard IP

Transceiver Banks

Altera Corporation

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