Altera Cyclone V Device Handbook page 938

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MWCR register. When MHS is set to 1, the SPI serial master checks for a ready status from the slave device
before completing the transfer, or transmitting the next control word for continuous transfers. †
After the first data word has been transmitted to the serial-slave device, the SPI master polls the rxd input
waiting for a ready status from the slave device. Upon reception of the ready status, the SPI master begins
transmission of the next control word. After transmission of the last data frame has completed, the SPI
master transmits a start bit to clear the ready status of the slave device before completing the transfer. †
In the SPI slave, data transmission begins with the falling edge of the slave select signal (ss_in_0). One-
half serial clock (sclk_in) period later, the first bit of the control is present on the rxd line. The length
of the control word can be in the range of 1 to 16 bits and is set by writing bit field CFS in the CTRLR0
register. The CFS bit field must be set to the size of the expected control word from the serial master. The
remainder of the control word is received (captured on the rising edge of sclk_in) by the SPI serial slave.
During this reception, no data are driven (high impedance) on the serial slave's txd line. †
The direction of the data word is controlled by the MDD bit field (bit 1) MWCR register. When MDD=0,
this indicates that the SPI serial slave is to receive data from the external serial master. Immediately after the
control word is transmitted, the serial master begins to drive the data frame onto the SPI slave rxd line.
Data are propagated on the falling edge of the serial clock and captured on the rising edge. The slave-select
signal is held active-low during the transfer and is deasserted one-half clock cycle later after the data are
transferred. The SPI slave output enable signal is held inactive for the duration of the transfer. †
When MDD=1, this indicates that the SPI serial slave transmits data to the external serial master. Immediately
after the LSB of the control word is transmitted, the SPI slave transmits a dummy 0 bit, followed by the 4-
to 16-bit data frame on the txd line. †
Continuous transfers for a SPI slave occur in the same way as those specified for the SPI master. The SPI
slave does not support the handshaking interface, as there is never a busy period. †
Figure 19-9: Single SPI Serial Master Microwire Serial Transfer (MDD=0)
Figure 19-10: Single SPI Slave Microwire Serial Transfer (MDD=1)
SPI Controller
Send Feedback
sclk_out
Control Word
txd
MSB
rxd
ssi_oe_n
sclk_out
txd
Control Word
MSB
rxd
ss_in_0
ssi_oe_n
National Semiconductor Microwire Protocol
LSB
4 - 16 Bits
MSB
Data Word
0 MSB
LSB
LSB
LSB
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