Altera Cyclone V Device Handbook page 816

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DMA Channel Thread in Secure State

When the CNS bit is 0, the DMA channel thread is programmed to operate in the Secure state and it only

performs secure instruction fetches.

When a DMA channel thread in the Secure state processes the following instructions:

• DMAWFE The DMAC halts execution of the thread until the event occurs. When the event occurs, the

DMAC continues execution of the thread, irrespective of the security state of the corresponding INS bit,

in the CR3 register.

• DMASEV The DMAC creates the event interrupt, irrespective of the security state of the corresponding

INS bit, in the CR3 register.

• DMAWFP The DMAC halts execution of the thread until the peripheral signals a DMA request. When

this occurs, the DMAC continues execution of the thread, irrespective of the security state of the

corresponding PNS bit, in the CR4 register.

• DMALDP and DMASTP The DMAC sends a message to the peripheral to communicate that data transfer

is complete, irrespective of the security state of the corresponding PNS bit, in the CR4 register.

• DMAFLUSHP The DMAC clears the state of the peripheral and sends a message to the peripheral to

resend its level status, irrespective of the security state of the corresponding PNS bit, in the CR4 register.

When a DMA channel thread is in the Secure state, it enables the DMAC to perform secure and non-secure

AXI accesses.

DMA Channel Thread in Non-Secure State

When the CNS bit is 1, the DMA channel thread is programmed to operate in the Non-secure state and it

only performs non-secure instruction fetches.

Altera Corporation

DMA Controller

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