Master Microwire Serial Transfers - Altera Cyclone V Device Handbook

19-20

Master Microwire Serial Transfers

6. The shift control logic stops the transfer when the transmit FIFO buffer is empty. If the transfer mode is
receive only (TMOD = 2'b10), the shift control logic stops the transfer when the specified number of
frames have been received. When the transfer is done, the BUSY status is reset to 0.
7. If the transfer mode is not transmit only (TMOD != 01), read the receive FIFO buffer until it is empty
8. Disable the SPI master by writing 0 to SSIENR.
Master Microwire Serial Transfers
Figure 19-12: Microwire Serial
To complete a Microwire serial transfer from the SPI master, follow these steps:
1. If the SPI master is enabled, disable it by writing 0 to SSIENR.
2. Set up the SPI control registers for the transfer. You can set these registers in any order.
Altera Corporation
Idle
Disable SPI
Configure Master by Writing
CTRLR0, CTRLR1, BAUDR,
TXFTLR, RXFTLR, MWCR,
IMR & SER
Enable SPI
If the master receives data, the user only
Write Control &
needs to write control frames into the TX
Data to Tx FIFO
FIFO. Transfer begins when the first control
word is present in the transmit FIFO and a
slave is enabled.
Transfer
in Progress
yes
Interrupt Service
Interrupt?
If the transmit FIFO makes the request
no
and all data has not been sent, write
data to the transmit FIFO.
If the receive FIFO makes the request,
read data from the receive FIFO.
Busy?
yes
no
Read Rx
FIFO
Routine
MWCR[1] = 1
cv_54019
2013.12.30
SPI Controller
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