Altera Cyclone V Device Handbook page 469

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Table 1-1: HPS Address Spaces

Address spaces are divided into one or more nonoverlapping contiguous regions. For example, the MPU

address space has the peripheral, FPGA slaves, SDRAM window, and boot regions.

The following figure shows the relationships between the HPS address spaces. The figure is not to scale.

Figure 1-3: HPS Address Space Relationships

The window regions provide access to other address spaces. The thin black arrows indicate which address

space is accessed by a window region (arrows point to accessed address space). For example, accesses to the

ACP window in the L3 address space map to a 1 GB region of the MPU address space.

The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue

vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to MPU

Address Space".

The ACP window can be mapped to any 1 GB region in the MPU address space (blue vertical bidirectional

arrow), on gigabyte-aligned boundaries.

The following table shows the base address and size of each region that is common to the L3 and MPU

address spaces.

Table 1-2: Common Address Space Regions

Introduction to Cyclone V Hard Processor System (HPS)

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MPU subsystem

L3 interconnect

SDRAM controller subsystem

Peripheral Region

Peripheral Region

(ROM/RAM/SDRAM)

Base Address

HPS Address Spaces

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