Transceiver Datapath Interface Clocking; Transmitter Datapath Interface Clocking - Altera Cyclone V Device Handbook

CV-53002
2013.05.06
Related Information
Clock Networks and PLLs in Cyclone V Devices

Transceiver Datapath Interface Clocking

There are two types of design considerations for clock optimization when interfacing the transceiver datapath
to the FPGA fabric:
• PCS with FIFO in phase compensation mode share clock network for identical channels
• PCS with FIFO in registered mode or PMA direct mode refer to AN 580: Achieving Timing Closure in
Basic (PMA Direct) Functional Mode, for additional timing closure techniques between transceiver and
FPGA fabric
The following sections describe design considerations for interfacing the PCS transmitter and PCS receiver
datapath to the FPGA fabric with FIFO in phase compensation mode.
Related Information
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode

Transmitter Datapath Interface Clocking

The write side of the TX phase compensation FIFO makes up the transmitter datapath interface. The
transmitter datapath interface clock clocks this interface.
The following figure shows the transmitter datapath interface clocking. The transmitter PCS forwards the
following clocks to the FPGA fabric:
• tx_clkout—for each transmitter channel in a non-bonded configuration
• tx_clkout[0]—for all transmitter channels in a bonded configuration
Figure 2-16: Transmitter Datapath Interface Clocking for Transceivers
All configurations that use the PCS channel must have a 0 parts per million (ppm) difference between write
and read clocks of the transmitter phase compensation FIFO.
Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom
Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices
chapters.
You can clock the transmitter datapath interface with one of the following options:
• The Quartus II-selected transmitter datapath interface clock
• The user-selected transmitter datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the user-
selection option to share the transceiver datapath interface clocks.
Transceiver Clocking in Cyclone V Devices
Send Feedback
Transmitter PCS
TX
Phase
Transmitter Data
Compensation
FIFO
Parallel Clock
Transceiver Datapath Interface Clocking
FPGA Fabric
tx_coreclkin
Transmitter Data
(User Selected Clock)
tx_clkout
(Quartus II Selected Clock)
tx_clkout
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