Altera Cyclone V Device Handbook page 676

10-38
Set Up a Single Area for Pipeline Read-Ahead
Similarly, you must write to all pages pertaining to pipeline write-ahead command before the next
pipeline command can be processed.
Since the value of the flag bit of the multiplane_operation register in the config group determines
pipeline read-ahead or write-ahead behavior, it can only be changed when the pipeline registers are empty.
When the host issues a pipeline read-ahead command, and the flash controller is idle, the load operation
happens immediately.
Note: The read-ahead command does not return the data to the host, and the write-ahead command does
not write data to the flash address. The NAND flash controller loads the read data. The read data is
returned to the host only when the host issues MAP01 commands to read the data. Similarly, the
flash controller loads the write data, and writes it to the flash only when the host issues MAP01
commands to write the data.
A pipe_cpyback_cmd_comp interrupt is generated when the NAND flash controller has finished
processing a pipeline command and has discarded that command from its queue. At this point of time, the
host can send another pipeline command. A pipeline command is popped from the queue, and an interrupt
is issued when the flash controller has started processing the last page of pipeline command. Hence, the
pipe_cpyback_cmd_comp interrupt is issued prior to the last page load in case of pipeline read command
and start of data transfer of the last page to be programmed in case of pipeline writes command.
An additional program_comp interrupt is generated when the last page program operation completes in
case of pipeline write command.
If the device command set requires the NAND flash controller to issue a load command for the last page in
the pipeline read command, a load_comp interrupt is generated after the last page load operation completes.
For pipeline write commands, if any page program results in a failure in the device, a program_fail
interrupt is issued. The failing page's block and page address is updated in the err_block_addr0 and
err_page_addr0 registers in the status group.
Pipeline commands sequence advanced commands in the device like cache and multi-plane. When the
NAND flash controller receives a multi-page read or write pipeline command, it sequences commands sent
to the device depending on settings in the following registers, in the config group:
• cache_read_enable
• cache_write_enable
• multiplane_operation
For a device that supports cache read sequences, the flag bit of the cache_read_enable register must
be set to 1. The NAND flash controller sequences each multi-page pipeline read command as a cache read
sequence. For a device that supports cache program command sequences, cache_write_enable must
be set. The flash controller sequences each multi-page write pipeline command as a cache write sequence.
For a device that has multi-planes and supports multi-plane program commands, the NAND flash controller
register multiplane_operation, in the config group, must be set. On receiving the multi-page
pipeline write command, the flash controller sequences the device with multi-plane program commands
and expects that the host transfers data to the flash controller in an even-odd block increment addressing
mode.
Set Up a Single Area for Pipeline Read-Ahead
To set up an area for pipeline read-ahead, perform the following steps:
Altera Corporation
cv_54010
2013.12.30
NAND Flash Controller
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