Altera Cyclone V Device Handbook page 971

20-20
Receive FIFO Overflow
In case 2: IC_DMA_TDLR = 48, the amount of space in the transmit FIFO at the time of the burst request
is made is equal to the DMA burst length. Thus, the transmit FIFO may be full, but not overflowed, at the
completion of the burst transaction. †
Therefore, for optimal operation, DMA burst length should be set at the FIFO level that triggers a transmit
DMA request; that is: †
DMA burst length = FIFO_DEPTH - IC_DMA_TDLR
Adhering to this equation reduces the number of DMA bursts needed for block transfer, and this in turn
improves bus utilization. †
The transmit FIFO will not be full at the end of a DMA burst transfer if the I
transmitted one data item or more on the I
Receive FIFO Overflow
2
During I C serial transfers, receive FIFO requests are made to the DMA whenever the number of entries in
the receive FIFO is at or above the DMA Receive Data Level Register, that is IC_DMA_RDLR + 1. This is
known as the watermark level. The DMA responds by fetching a burst of data from the receive FIFO. †
Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continuously,
that is, when the FIFO begins to fill, another DMA transfer is requested. Otherwise the FIFO will fill with
data (overflow). To prevent this condition, the user must set the watermark level correctly. †
Receive Watermark Level
Similar to choosing the transmit watermark level described earlier, the receive watermark level, IC_
DMA_RDLR + 1, should be set to minimize the probability of overflow, as shown in the Receive FIFO Buffer
diagram. It is a trade off between the number of DMA burst transactions required per block versus the
probability of an overflow occurring. †
Receive FIFO Underflow
Setting the source transaction burst length greater than the watermark level can cause underflow where there
is not enough data to service the source burst request. Therefore, the following equation must be adhered
to avoid underflow: †
DMA burst length = IC_DMA_RDLR + 1
If the number of data items in the receive FIFO is equal to the source burst length at the time of the burst
request is made, the receive FIFO may be emptied, but not underflowed, at the completion of the burst
transaction. For optimal operation, DMA burst length should be set at the watermark level, IC_DMA_RDLR
+ 1. †
Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can avoid
underflow and improve bus utilization. †
Note: The receive FIFO will not be empty at the end of the source burst transaction if the I
has successfully received one data item or more on the I
Altera Corporation
2
C serial transmit line during the transfer. †
2
C serial receive line during the burst. †
2
C controller has successfully
2
C controller
I2C Controller
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2013.12.30