Altera Cyclone V Device Handbook page 365

CV-53002
2013.05.06
Selecting a Receiver Datapath Interface Clock
Multiple non-bonded receiver channels use a large portion of GCLK, RCLK, and PCLK resources. Selecting
a common clock driver for the receiver datapath interface of all identical receiver channels saves clock
resources.
Non-bonded multiple receiver channels lead to high utilization of GCLK, RCLK, and PCLK resources (one
clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource use for the
receiver datapath clocks if the receiver channels are identical.
Note: Identical receiver channels are defined as channels that have the same input reference clock source
for the CDR and the same receiver PMA and PCS configuration. These channels may have different
analog settings, such as receiver common mode voltage (V
To achieve clock resource savings, select a common clock driver for the receiver datapath interface of all
identical receiver channels. To select a common clock driver, perform these steps:
1. Instantiate the rx_coreclkin port for all the identical receiver channels
2. Connect the common clock driver to their receiver datapath interface, and receiver data and control
logic.
The following figure shows six identical channels that are clocked by a single clock (rx_clkout[0]).
Figure 2-23: Six Identical Channels with a Single User-Selected Receiver Interface Clock
Transceiver Clocking in Cyclone V Devices
Send Feedback
Receiver Standard PCS
Channel 7
Channel 6
Channel 5
Channel 4
rx_clkout[4]
Channel 3
Channel 2
Channel 1
Channel 0
Selecting a Receiver Datapath Interface Clock
), equalization, or DC gain setting.
ICM
FPGA Fabric
rx_coreclkin[7]
rx_coreclkin[6]
rx_coreclkin[5]
rx_coreclkin[4]
Channel [7:0] Receiver
Data and Control Logic
rx_coreclkin[3]
rx_coreclkin[2]
rx_coreclkin[1]
rx_coreclkin[0]
2-27
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