Altera Cyclone V Device Handbook page 656

10-18
Out-Of-Order DMA Commands
Table 10-10: Transaction 1 Data
Reserved
Table 10-11: Transaction 2 Address Encoding
31:28 27:26 25:24
0x0 0x2 Res.
Table 10-12: Transaction 2 Data
Reserved
Table 10-13: Transaction 3 Address Encoding
31:28 27:26 25:24
0x0 0x2 Res.
Table 10-14: Transaction 3 Data
Reserved
Table 10-15: Transaction 4 Address Encoding
31:28 27:26 25:24
0x0 0x2 Res.
Table 10-16: Transaction 4 Data
Reserved
Related Information
Multitransaction DMA Commands
Out-Of-Order DMA Commands
The flash controller ignores out-of-order DMA commands. If transactions are not in the expected order,
the flash controller resets itself to the initial state and generates an un_sup interrupt. Any other transactions
in between command-DMA MAP10 commands cause the flash controller to ignore the command-DMA
Altera Corporation
31:16
Descriptor address high (Most significant 16 bits)
31:16
Descriptor address Low (Least significant 16 bits)
31:16
Reserved
31:16
on page 10-17
15:8
0x0
23:8
15:8
0x0
23:8
15:8
0x0
23:8
15:8
0x0
cv_54010
2013.12.30
7:6 5:0
0x2 Channel number
7:0
0x0
7:4 3:0
0x9 0x0
7:0
0x0
7:4 3:0
0xa 0x0
7:0
0x0
7:4 3:0
0xb 0x0
NAND Flash Controller
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