External Memory Interface Datapath; Dqs Phase-Shift Circuitry - Altera Cyclone V Device Handbook

CV-52006
2014.01.10
Related Information
Reference Material volume, External Memory Interface Handbook
Provides more information about the UniPHY IP.

External Memory Interface Datapath

The following figure shows an overview of the memory interface datapath that uses the Cyclone V I/O
elements. In the figure, the DQ/DQS read and write signals may be bidirectional or unidirectional, depending
on the memory standard. If the signal is bidirectional, it is active during read and write operations. You can
bypass each register block.
Figure 6-1: External Memory Interface Datapath Overview for Cyclone V Devices

DQS Phase-Shift Circuitry

The Cyclone V DLL provides phase shift to the DQS pins on read transactions if the DQS pins are acting as
input clocks or strobes to the FPGA.
The following figures show how the DLLs are connected to the DQS pins in the various Cyclone V variants.
The reference clock for each DLL may come from adjacent PLLs.
Note: The following figures show all possible connections for each device. For available pins and connections
in each device package, refer to the device pin-out files.
External Memory Interfaces in Cyclone V Devices
Send Feedback
FPGA
Postamble Clock
Full-Rate Clock
Clock
DQ Write Clock
Management
and Reset Half-Rate Clock
DQS Write Clock
Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.
Postamble Enable
DQS Delay
DLL
Chain
4n or 2n
2n
Read FIFO
4n
Half Data
2n
Rate
Output
Registers
Half Data
4
2
Rate
Output
Registers
External Memory Interface Datapath
Memory
DQS Postamble
Circuitry
DQS Enable
Control
Circuit
DQS
DQS (Read)
Enable
Circuit
DDR Input
n
Registers
DQ (Read)
DDR Output
n
and Output
DQ (Write)
Enable
Registers
DDR Output
and Output
DQS (Write)
Enable
Registers
6-13
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