Singleport Sdram Controller Operational Behavior; Command And Data Reordering; Bank Policy - Altera Cyclone V Device Handbook

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2013.12.30
Clocking
The FPGA fabric ports of the MPFE can be clocked at different frequencies. Synchronization is maintained
by clock-domain crossing logic in the MPFE. Command ports can operate on different clock domains, but
the data ports associated with a given command port must be attached to the same clock as that command
port. For example, a command port paired with a read and write port to form an Avalon-MM interface must
operate at the same clock frequency as the data ports associated with it.

SinglePort SDRAM Controller Operational Behavior

This section describes the operational behavior of the single-port controller.
SDRAM Interface
The SDRAM interface is up to 40 bits wide and can accommodate 8-bit, 16-bit, 16-bit plus ECC, 32-bit, or
32-bit plus ECC configurations. The SDRAM interface supports LPDDR2, DDR2, and DDR3 memory
protocols.

Command and Data Reordering

The heart of the SDRAM controller is a command and data reordering engine. Command reordering allows
banks for future transactions to be opened before the current transaction finishes.
Data reordering allows transactions to be serviced in a different order than they were received when that
new order allows for improved utilization of the SDRAM bandwidth. Operations to the same bank and row
are performed in order to ensure that operations which impact the same address preserve the data integrity.
The following figure shows the relative timing for a write/read/write/read command sequence performed
in order and then the same command sequence performed with data reordering. Data reordering allows the
write and read operations to occur in bursts, without bus turnaround timing delay or bank reassignment.
Figure 8-3: Data Reordering Effect
The SDRAM controller schedules among all pending row and column commands every clock cycle.

Bank Policy

The bank policy of the SDRAM controller allows users to request that a transaction's bank remain open after
an operation has finished so that future accesses do not delay in activating the same bank and row
combination. The controller supports only eight simultaneously-opened banks, so an open bank might get
closed if the bank resource is needed for other operations.
Open bank resources are allocated dynamically as SDRAM burst transactions are scheduled. Bank allocation
is requested automatically by the controller when an incoming transaction spans multiple SDRAM bursts
or by the extended command interface. When a bank must be reallocated, the least-recently-used open bank
is used as the replacement.
SDRAM Controller Subsystem
Send Feedback
Data Reordering Off
Command WR
Address B0R0
Data Reordering On
Command WR WR
Address B0R0 B0R0
SinglePort SDRAM Controller Operational Behavior
RD WR
B1R0 B0R0
RD RD
B1R0 B1R0
8-9
RD
B1R0
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