Altera Cyclone V Device Handbook page 503

cv_54003
2013.12.30
Module Reset Signal
spim_rst_n[1:0]
spis_rst_n[1:0]
sdmmc_rst_n
can_rst_n[1:0]
gpio_rst_n[2:0]
dma_rst_n
sdram_rst_n
Table 3-5: PER2 Group, Generated Module Resets
Module Reset Signal
dma_periph_if_rst_n[7:0]
Table 3-6: Bridge Group, Generated Module Resets
Module Reset Signal
hps2fpga_bridge_rst_n
fpga2hps_bridge_rst_n
lwhps2fpga_bridge_rst_n
Table 3-7: MISC Group, Generated Module Resets
Module Reset Signal
boot_rom_rst_n
onchip_ram_rst_n
sys_manager_rst_n
Reset Manager
Send Feedback
Description
Resets SPI master controller
Resets SPI slave controller
Resets SD/MMC controller
Resets each CAN controller
Resets each GPIO interface
Resets DMA controller
Resets SDRAM subsystem
(resets logic associated with
cold or warm reset)
Description
DMA controller request
interface from FPGA fabric
to DMA controller
Description
Resets HPS-to-FPGA
®
AMBA Advanced
eXtensible Interface (AXI
bridge
Resets FPGA-to-HPS AXI
bridge
Resets lightweight HPS-to-
FPGA AXI bridge
Description
Resets boot ROM
Resets on-chip RAM
Resets system manager
(resets logic associated with
cold or warm reset)
Module Reset Signals
Reset Cold Warm
Domain Reset Reset
System X X
System X X
System X X
System X X
System X X
System X X
System X X
Reset Cold Warm
Domain Reset Reset
System X X
Reset Cold Warm
Domain Reset Reset
System X X
™
)
System X X
System X X
Reset Cold Warm
Domain Reset Reset
System X X
System X X
System X X
3-7
Debug Software
Reset Deassert
X
X
X
X
X
X
X
Debug Software
Reset Deassert
X
Debug Software
Reset Deassert
X
X
X
Debug Software
Reset Deassert
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