Altera Cyclone V Device Handbook page 199

CV-52006
2014.01.10
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input DQS signals to be shifted by
the amount specified by the DQS phase-shift circuitry or the logic array.
There are two delay elements in the DQS delay chain that have the same characteristics:
Delay elements in the DQS logic block
Delay elements in the DLL
The DQS pin is shifted by the DQS delay settings.
The number of delay chains required is transparent because the UniPHY IP automatically sets it when you
choose the operating frequency.
In the Cyclone V SE, SX, and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry
only.
Related Information
ALTDQ_DQS2 Megafunction User Guide
Provides more information about programming the delay chains.
Delay Chains
DQS Postamble Circuitry
There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2
SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during
the end of a read operation that occurs while DQS is in a postamble state.
The Cyclone V devices contain dedicated postamble registers that you can control to ground the shifted
DQS signal that is used to clock the DQ input registers at the end of a read operation. This function ensures
that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in
a postamble state do not affect the DQ IOE registers.
For preamble state, the DQS is low, just after a high-impedance state.
For postamble state, the DQS is low, just before it returns to a high-impedance state.
For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS
signal is low before going to or coming from a high-impedance state.
Half Data Rate Block
The Cyclone V devices contain a half data rate (HDR) block in the postamble enable circuitry.
The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock
divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from
a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for
dqsenable
Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.
Altera recommends using these registers if the controller is running at half the frequency of the I/Os.
External Memory Interfaces in Cyclone V Devices
Send Feedback
on page 6-28
assertion and zero latency for deassertion.
dqsenable
6-25
DQS Delay Chain
Altera Corporation