Passive Serial Single-Device Configuration Using An External Host; Passive Serial Single-Device Configuration Using An Altera Download Cable - Altera Cyclone V Device Handbook

Hide thumbs Also See for Cyclone V:
Table of Contents

Advertisement

CV-52007
2014.01.10
the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000
0111-0111 1000-0000 0101-1111.
You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the
flash memory device and configure the Cyclone V device.
For a PC host, connect the PC to the device using a download cable such as the Altera USB-Blaster USB
port, ByteBlaster II parallel port, EthernetBlaster, and EthernetBlaster II download cables.
The configuration data is shifted serially into the
If you are using the Quartus II programmer and the
clock source for the pin to initialize your device.
Related Information
Parallel Flash Loader Megafunction User Guide
Cyclone V Device Datasheet
Provides more information about the PS configuration timing.

Passive Serial Single-Device Configuration Using an External Host

To configure a Cyclone V device, connect the device to an external host, as shown in the following figure.
Figure 7-12: Single Device PS Configuration Using an External Host

Passive Serial Single-Device Configuration Using an Altera Download Cable

To configure a Cyclone V device, connect the device to a download cable, as shown in the following figure.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Send Feedback
Passive Serial Single-Device Configuration Using an External Host
Memory
V
V
CCPGM
CCPGM
ADDR
DATA0
10 kΩ
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
pin of the device.
DATA0
pin is enabled, you do not need to provide a
CLKUSR
Connect the resistor to a power supply that provides an acceptable
input signal for the FPGA device. V
meet the V
specification of the I/O on the device and the external
IH
host. Altera recommends powering up all the configuration system
I/Os with V
.
CCPGM
FPGA Device
CONF_DONE
nSTATUS
nCE
nCEO
N.C.
GND
DATA0
nCONFIG
DCLK
MSEL[4..0]
must be high enough to
CCPGM
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device's nCE pin.
For more information, refer to
the MSEL pin settings.
Altera Corporation
7-21

Advertisement

Table of Contents
loading

Table of Contents