Delay Chains - Altera Cyclone V Device Handbook

6-28

Delay Chains

Figure 6-18: IOE Output and Output-Enable Path Registers for Cyclone V Devices
The following figure shows the registers available in the Cyclone V output and output-enable paths.
Data coming from the FPGA core are at half the frequency of the
memory interface clock frequency in half-rate mode
From Core
From Core
From Core
(wdata2)
From Core
(wdata0)
From Core
(wdata3)
From Core
(wdata1)
Half-Rate Clock
from PLL
Delay Chains
The Cyclone V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks.
You can control the delay chain setting through the I/O or the DQS configuration block output.
Every I/O block contains a delay chain between the following elements:
The output registers and output buffer
The input buffer and input register
The output enable and output buffer
The R OCT enable-control register and output buffer
T
You can bypass the DQS delay chain to achieve a 0° phase shift.
Altera Corporation
Half Data Rate to Single
Data Rate Output-Enable
Registers
0
Q
D
1
DFF
Q
D
DFF
Half Data Rate to Single
Data Rate Output Registers
D Q
0
1
DFF
Q
D
DFF
0
D Q
1
DFF
Q
D
DFF
Write Clock
Double Data Rate
Output-Enable Registers
Q
D
DFF
OE Reg A
1
OE
0
Q
D
DFF
OE Reg B
OE
Double Data Rate
Output Registers
D Q 0
1
DFF
OE Reg A
O
D Q
DFF
OE Reg B
O
The full-rate write clock can come from the PLL. The DQ
write clock have a 90° offset to the DQS write clock.
External Memory Interfaces in Cyclone V Devices
OR2
DQ or DQS
TRI
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CV-52006
2014.01.10