Offset Cancellation; Transmitter Duty Cycle Distortion Calibration - Altera Cyclone V Device Handbook

7-2

Offset Cancellation

Reconfiguration Feature
Data Rate Change
Related Information
• Backplane Applications with 28 nm FPGAs
• AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and
ALTERA_PLL_RECONFIG Megafunctions
For information about reconfiguration of the fPLL data rate.
Offset Cancellation
Offset cancellation adjusts the offsets within the CDR parameters for process variations.
Every transceiver channel has offset cancellation circuitry to compensate for the offset variations that are
caused by process operations. The offset cancellation circuitry is controlled by the offset cancellation control
logic IP within the Transceiver Reconfiguration Controller. Resetting the Transceiver Reconfiguration
Controller during user mode does not trigger the offset cancellation process.
When offset cancellation calibration is complete, the reconfig_busy status signal is deasserted to indicate
the completion of the process.
The clock (mgmt_clk_clk) used by the Transceiver Reconfiguration Controller is also used for transceiver
calibration and must be 75-125 MHz if the Hard IP for PCIe Express IP core is not enabled. When the Hard
IP for PCIe Express is enabled, the frequency range is 75-100 MHz. If the clock (mgmt_clk_clk) is not
free-running, hold the reconfiguration controller reset (mgmt_rst_reset) until the clock is stable.

Transmitter Duty Cycle Distortion Calibration

The duty cycle calibration function tunes the transmitter to minimize duty cycle distortion.
Altera Corporation
Description
Increase or decrease the
data rate (/1, /2, /4, /8) for
autonegotiation purposes
such as CPRI and SATA/
SAS applications
Reconfigure the TX PLL
settings for protocols with
multi-data rate support
such as CPRI
Switch between multiple TX
PLLs for multi-data rate
support
Channel
reconfiguration—Reconfigure
the RX CDR from one data
rate to another data rate
Affected Blocks
TX Local clock dividers
TX PLL
• TX PLL
• Fractional PLL (Reconfigure the
fPLL data rate with the ALTERA_
PLL_RECONFIG megafunction.)
CDR
Dynamic Reconfiguration in Cyclone V Devices
CV-53007
2013.05.06
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