Clocks And Resets; Resets - Altera Cyclone V Device Handbook

17-22
Unmatched Frames
matches, the MAC provides status of the lowest filter with filter 0 being the lowest and filter 3 being the
highest. For example, if filter 0 and filter 1 match, the MAC gives the status corresponding to filter 0.
Unmatched Frames
The MAC drops the frames that do not match any of the enabled fields. You can use the inverse match
feature to block or drop a frame with specific TCP or UDP over IP fields and forward all other frames. You
can configure the EMAC so that when a frame is dropped, it receives a partial frame with appropriate abort
status or drops it completely.
NonTCP or UDP IP Frames
By default, all non-TCP or UDP IP frames are bypassed from the Layer 3 and Layer 4 filters. You can
optionally program the MAC to drop all non-TCP or UDP over IP frames.

Clocks and Resets

Table 17-6: Ethernet MAC Controller Clocks
Name
clk_ref_i
clk_tx_i
clk_rx_i
Clock Gating for EEE
For the RGMII PHY interface, you can gate the transmit clock for Energy Efficient Ethernet (EEE) applications.
Related Information
Programming Guidelines for Energy Efficient Ethernet

Resets

Table 17-7: Ethernet MAC Controller Reset Signals
Name
rst_clk_tx_n_o
rst_clk_rx_n_o
Altera Corporation
†
Nominal
Frequency
250 Mhz Reference Clock to the EMAC
125/25/2.5 MHz Auto negotiates speed down to 10/
100 Mbps
PHY provides this reference to
MAC
Functional Usage
Transmit clock reset output
Receive clock reset output
Functional Usage
on page 17-55
Used to reset external PHY transmit
clock domain logic
Used to reset external PHY receive
clock domain logic
†
Notes
If supplied from clock
interface, clock is emac0_clk or
emac1_clk
All PHY signals received by the
MAC are synchronous to this
clock
Notes
Ethernet Media Access Controller
Send Feedback
cv_54017
2013.12.30
†