Clock Networks And Plls In Cyclone V Devices; Clock Networks - Altera Cyclone V Device Handbook

Clock Networks and PLLs in Cyclone V Devices

2014.01.10
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This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs)
in Cyclone V devices. The Quartus II software enables the PLLs and their features without external devices.
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.

Clock Networks

The Cyclone V devices contain the following clock networks that are organized into a hierarchical structure:
Global clock (GCLK) networks
Regional clock (RCLK) networks
Periphery clock (PCLK) networks
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