Altera Cyclone V Device Handbook page 328

CV-53001
2013.05.06
Programmable Run-Length Violation Detection
The programmable run-length violation detection circuit resides in the word aligner block and detects if
consecutive 1s or 0s in the received data exceed the user-specified threshold.
If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by
the assertion of the rx_rlv status bit.
Table 1-24: Detection Capabilities of the Run-Length Violation Circuit
PCS Mode
Single Width
Double Width
Receiver Polarity Inversion
The positive and negative signals of a serial differential link might erroneously be swapped during board
layout. Solutions such as board re-spin or major updates to the PLD logic can be expensive. The polarity
inversion feature at the receiver corrects the swapped signal error without requiring board re-spin or major
updates to the logic in the FPGA fabric. The polarity inversion feature inverts the polarity of every bit at the
input to the word aligner, which has the same effect as swapping the positive and negative signals of the
serial differential link.
Inversion is controlled dynamically with the rx_invpolarity register. When you enable the polarity
inversion feature, initial disparity errors may occur at the receiver with the 8B/10B-coded data. The receiver
must be able to tolerate these disparity errors.
Caution:
Bit Reversal
By default, the receiver assumes a LSB-to-MSB transmission. If the transmission order is MSB-to-LSB, the
receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on rx_parallel_data.
To reverse the bit order at the output of the word aligner to receive a MSB-to-LSB transmission, use the bit
reversal feature at the receiver.
Table 1-25: Bit Reversal Feature
Bit Reversal Option
Disabled (default)
Transceiver Architecture in Cyclone V Devices
Send Feedback
PMA PCS Interface
Width (bits)
If you enable polarity inversion midway through a word, the word will be corrupted.
Single-Width Mode (8 or 10 bit)
LSB to MSB
Programmable Run-Length Violation Detection
Run-Length Violation Detector Range
Minimum
8 4
10 5
16 8
20 10
Received Bit Order
LSB to MSB
Maximum
128
160
512
640
Double-Width Mode (16 or 20 bit)
1-41
Altera Corporation