Multiple Master Arbitration - Altera Cyclone V Device Handbook

20-8
START BYTE Transfer Protocol
Related Information
Combined Formats
START BYTE Transfer Protocol
The START BYTE transfer protocol is set up for systems that do not have an on-board dedicated I
module. When the I
so that it never requires a START BYTE transfer. However, when I
the generation of START BYTE transfers at the beginning of every transfer in case a slave device requires
it. This protocol consists of seven zeros being transmitted followed by a 1, as illustrated in the following
figure. This allows the processor that is polling the bus to under-sample the address phase until the
microcontroller detects a 0. Once the microcontroller detects a 0, it switches from the under sampling rate
to the correct rate of the master. †
Figure 20-8: START BYTE Transfer †
SDA
SCL
The START BYTE has the following procedure: †
1. Master generates a START condition. †
2. Master transmits the START byte (0000 0001). †
3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on
the bus) †
4. No slave sets the ACK signal to 0. †
5. Master generates a RESTART (R) condition. †
A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after
the RESTART condition is generated. †

Multiple Master Arbitration

2
The I C controller bus protocol allows multiple masters to reside on the same bus. If there are two masters
2
on the same I C-bus, there is an arbitration procedure if both try to take control of the bus at the same time
by simultaneously generating a START condition. Once a master (for example, a microcontroller) has control
of the bus, no other master can take control until the first master sends a STOP condition and places the
bus in an idle state. †
Arbitration takes place on the SDA line, while the SCL line is 1. The master, which transmits a 1 while the
other master transmits 0, loses arbitration and turns off its data output stage. The master that lost arbitration
can continue to generate clocks until the end of the byte transfer. If both masters are addressing the same
slave device, the arbitration could go into the data phase. †
Upon detecting that it has lost arbitration to another master, the I
The following figure illustrates the timing of two masters arbitrating on the bus.
Altera Corporation
on page 20-4
2
C controller is set as a slave, it always samples the I
S
1 2
Start Byte 00000001
2
C bus at the highest speed supported
2
C controller is set as a master, it supports
Dummy Acknowledge
(High)
7 8 9
ACK
2
C controller stops generating SCL. †
2013.12.30
2
C hardware
Sr
I2C Controller
Send Feedback
cv_54020