Document Revision History - Altera Cyclone V Device Handbook

1-18

Document Revision History

Slave Identifier
OSC1TIMER1
L4WD0
L4WD1
CLKMGR
RSTMGR
SYSMGR
DMANONSECURE
DMASECURE
SPIS0
SPIS1
SPIM0
SPIM1
SCANMGR
ROM
MPUSCU
MPUL2
OCRAM
Document Revision History
Table 1-6: Document Revision History
Date
December 2013
November 2012
June 2012
May 2012
January 2012
Altera Corporation
Slave Title
OSC1 Timer1
Watchdog0
Watchdog1
Clock manager
Reset manager
System manager
DMA nonsecure registers
DMA secure registers
SPI slave0
SPI slave1
SPI master0
SPI master1
Scan manager registers
Boot ROM
MPU SCU registers
MPU L2 cache controller
registers
On-chip RAM
2013.12.30
1.3
1.2
1.1
1.0
Base Address
0xFFD01000
0xFFD02000
0xFFD03000
0xFFD04000
0xFFD05000
0xFFD08000
0xFFE00000
0xFFE01000
0xFFE02000
0xFFE03000
0xFFF00000
0xFFF01000
0xFFF02000
0xFFFD0000
0xFFFEC000
0xFFFEF000
0xFFFF0000
Version
Maintenance release
Minor updates.
Updated address spaces section.
Added peripheral region address
map.
Initial release.
Introduction to Cyclone V Hard Processor System (HPS)
cv_54001
2013.12.30
Size
4 KB
4 KB
4 KB
4 KB
4 KB
16 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
64 KB
8 KB
4 KB
64 KB
Changes
Send Feedback