Receiver Clocking For Cyclone V Devices; Differential I/O Termination For Cyclone V Devices - Altera Cyclone V Device Handbook

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Receiver Clocking for Cyclone V Devices

You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. The

clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.

The following figure shows the LVDS datapath block diagram. In SDR and DDR modes, the data width from

the IOE is 1 and 2 bits, respectively.

Figure 5-42: Receiver Data Path in LVDS Mode

Receiver Clocking for Cyclone V Devices

The fractional PLL receives the external clock input and generates different phases of the same clock.

The physical medium connecting the transmitter and receiver LVDS channels may introduce skew between

the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and

the clock also varies with the jitter on the data and clock signals as seen by the receiver.

LVDS mode allows you to statically select the optimal phase between the source synchronous clock and the

received serial data to compensate skew.

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

The Cyclone V devices provide a 100 Ω, on-chip differential termination option on each differential receiver

channel for LVDS standards. On-chip termination saves board space by eliminating the need to add external

resistors on the board. You can enable on-chip termination in the Quartus II software Assignment Editor.

All I/O pins and dedicated clock input pins support on-chip differential termination, R

Altera Corporation

IOE supports SDR, DDR, or non-registered datapath

Deserializer

LVDS Clock Domain

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

Fractional PLL

Note: All disabled blocks and signals are grayed out

on page 5-12

LVDS_diffioclk

LVDS Receiver

rx_inclock / tx_inclock

I/O Features in Cyclone V Devices

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