Fast Passive Parallel Configuration; Fast Passive Parallel Single-Device Configuration - Altera Cyclone V Device Handbook

CV-52007
2014.01.10
Related Information
Reviewing Printed Circuit Board Schematics with the Quartus II Software
Provides more information about the device and pin options dialog box setting.

Fast Passive Parallel Configuration

The FPP configuration scheme uses an external host, such as a microprocessor, MAX
device. This scheme is the fastest method to configure Cyclone V devices. The FPP configuration scheme
supports 8- and 16-bits data width.
You can use an external host to control the transfer of configuration data from an external storage such as
flash memory to the FPGA. The design that controls the configuration process resides in the external host.
You can store the configuration data in Raw Binary File (.rbf), Hexadecimal (Intel-Format) File (.hex), or
Tabular Text File (.ttf) formats.
You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the
flash memory device and configure the Cyclone V device.
Note: Two
the device for both uncompressed and compressed configuration data in an FPP configuration.
Related Information
Parallel Flash Loader Megafunction User Guide
Cyclone V Device Datasheet
Provides more information about the FPP configuration timing.

Fast Passive Parallel Single-Device Configuration

To configure a Cyclone V device, connect the device to an external host as shown in the following figure.
Figure 7-2: Single Device FPP Configuration Using an External Host
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Send Feedback
falling edges are required after the
DCLK
Connect the resistor to a supply that
provides an acceptable input signal
for the FPGA device. V
high enough to meet the V
specification of the I/O on the device
and the external host. Altera
recommends powering up all
configuration system I/Os with V
Memory
ADDR DATA[7..0]
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
CONF_DONE
must be
CCPGM
IH
.
CCPGM
V V
CCPGM CCPGM
FPGA Device
10 kΩ
MSEL[4..0]
CONF_DONE
nSTATUS
nCE
GND
DATA[]
nCONFIG
DCLK
Fast Passive Parallel Configuration
®
pin goes high to begin the initialization of
For more information, refer to
the MSEL pin settings.
nCEO N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device's nCE pin.
7-9
II device, or MAX V
Altera Corporation