Transmitter Clocking - Altera Cyclone V Device Handbook

CV-53002
2013.05.06
The contiguous channels may span across many banks for bonded mode. For example, in x8 bonding,
the bonded channels may span across 3 to 4 banks with the condition that there must be no gap
between the channels except when the gap is due to the channel used for CMU PLL.

Transmitter Clocking

Transmitter (TX) clocking refers to the clocking architecture that is internal to the TX channel of a transceiver.
As shown in the following figure, the clock divider provides the serial clock to the serializer, and the parallel
clock to the serializer and TX PCS. When the byte serializer is not used, the parallel clock clocks all the blocks
up to the read side of the TX phase compensation FIFO. For configurations with the byte serializer, the
parallel clock is divided by a factor of two for the byte serializer and the read side of the TX phase
compensation FIFO. The read side clock of the TX phase compensation FIFO is also forwarded to the FPGA
fabric to interface the FPGA fabric with the transceiver.
Figure 2-8: Clocking Architecture for Transmitter PCS and PMA Configuration
Transmitter PMA
Local/Central
clock divider
Both Parallel and Serial Clocks
Serial Clock
Parallel Clock
Data Path
Transmitter
Table 2-5: Clock Sources for All TX PCS Blocks
PCS Block
TX Phase Compensation
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Non-Bonded Channel Configurations
This section describes the clock path for non-bonded configurations.
The following table describes the clock path for non-bonded configuration with the CMU PLL and fPLL as
TX PLL using various clock lines.
Transceiver Clocking in Cyclone V Devices
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Transmitter PCS
Side
Write FPGA fabric write clock, driven either by tx_clkout or tx_
coreclkin
Read Parallel clock (divided). Clock forwarded to FPGA fabric as tx_
clkout
Write Parallel clock (divided) either by factor of 1 (not enabled), or
factor of 2 (enabled)
Read Parallel clock
— Parallel clock
— Parallel clock
Transmitter Clocking
FPGA Fabric
tx_parallel_data
tx_coreclkin /
tx_std_coreclkin
/2
tx_clkout /
tx_std_clkout
Clock Source
2-9
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