Gigabit Ethernet Transceiver Datapath - Altera Cyclone V Device Handbook

CV-53004
2013.10.17
Figure 4-13: Transceiver Blocks in a GbE Configuration

Gigabit Ethernet Transceiver Datapath

Figure 4-14: Transceiver Datapath in GbE-1.25 Gbps Configuration
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
Functional Mode
PMA-PCS Interface Width
Data Rate (Gbps)
Number of Bonded Channels
Low Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-Transceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
FPGA Fabric
TX Phase
Compensation
FIFO
wrclk rdclk
tx_coreclk[0]
tx_clkout[0]
FPGA Fabric–Transceiver Interface Clock
RX Phase
Compensation
FIFO
rx_coreclk[0]
Gigabit Ethernet Transceiver Datapath
Gbe
10 bit
1.25
x1
Disabled
Automatic Synchronization
State Machine
(7-bit Comma, 10-bit /K28.5/)
Enabled
Enabled
Disabled
Disabled
8-bit
125
Transmitter Channel PCS
8B/10B
Encoder
Low-Speed Parallel Clock
Receiver Channel PCS
Rate
8B/10B Word
Match
Decoder Aligner
FIFO
Parallel Recovered Clock
Low-Speed Parallel Clock
3.125
x1
Disabled
Automatic Synchronization
State Machine
(7-bit Comma, 10-bit /K28.5/)
Enabled
Enabled
Enabled
Disabled
16-bit
156.25
Transmitter Channel PMA
Serializer
High-Speed Serial Clock
Local Clock
Divider
Receiver Channel PMA
Deserializer CDR
4-13
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