Altera Cyclone V Device Handbook page 233

7-18
Programming EPCS Using the Active Serial Interface
Figure 7-9: Connection Setup for Programming the EPCQ Using the JTAG Interface
EPCQ Device
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
Programming EPCS Using the Active Serial Interface
To program an EPCS device using the AS interface, connect the device as shown in the following figure.
Altera Corporation
V V V
CCPGM CCPGM CCPGM
10 kΩ 10 kΩ 10 kΩ
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
AS_DATA0/ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCSO
Instantiate SFL in your
design to form a bridge
between the EPCQ and
the 10-pin header.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
V V
CCPD CCPD
TCK
TDO
TMS
TDI
Pin 1
Serial
Flash
1 kΩ
Loader
MSEL[4..0]
CLKUSR
Download Cable
GND
10-Pin Male Header
(JTAG Mode) (Top View)
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply the external clock
source to drive DCLK during configuration.
Connect the pull-up resistors to
V at a 3.0- or 3.3-V
CCPGM
power supply.
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for your
V
CCPD
setup.
GND
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CV-52007
2014.01.10