Altera Cyclone V Device Handbook page 368

3-2
Embedded Reset Controller Signals
Figure 3-1: Embedded Reset Controller
Transceiver PHY
phy_mgmt_clk
phy_mgmt_clk_reset
Avalon-MM
Table 3-1: Embedded Reset Controller Reset Control and Status Signals
Signal Name
phy_mgmt_clk
phy_mgmt_clk_reset
tx_ready
rx_ready
Altera Corporation
Receiver Transmitter
PCS PCS
rx_digitalreset
tx_digitalreset
Embedded Reset Controller
Avalon-MM
PHY Management
Interface
S M
Signal
Control Input
Control Input
Status Output
Status Output
Transmitter
Receiver
PMA
Transmitter
CDR
pll_is_locked
rx_is_lockedtodata
rx_analogreset
PCS and PMA Control
and Status Register
Memory Map
S
Clock for the embedded reset controller.
A high-to-low transition of this asynchronous reset
signal initiates the automatic reset sequence control.
Hold this signal high to keep the reset signals asserted.
A continuous high on this signal indicates that the
transmitter (TX) channel is out of reset and is ready
for data transmission. This signal is synchronous to
phy_mgmt_clk.
A continuous high on this signal indicates that the
receiver (RX) channel is out of reset and is ready for
data reception. This signal is synchronous to phy_
mgmt_clk.
PMA
PLL
pll_powerdown
tx_analogreset
tx_ready
rx_ready
pll_locked
rx_is_lockedtodata
rx_is_lockedtoref
reconfig_to_xcvr
reconfig_from_xcvr
Description
Transceiver Reset Control in Cyclone V Devices
CV-53003
2013.05.06
reconfig_busy
Transceiver
Reconfiguration
Controller
mgmt_rst_reset
mgmt_clk_clk
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