Transceiver Clocking In Cyclone V Devices; Input Reference Clocking - Altera Cyclone V Device Handbook

2013.05.06
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This chapter provides information about the Cyclone
describes the clocks that are required for operation, internal clocking architecture, and clocking options
when the transceiver interfaces with the FPGA fabric.
Figure 2-1: Transceiver Clocking Architecture Overview
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.

Input Reference Clocking

This section describes how the reference clock for the transmitter PLL and CDR is provided to generate the
clocks required for transceiver operation.
Table 2-1: Input Reference Clock Sources
Sources
Dedicated refclk pin
REFCLK network
Dual-purpose RX / refclk pin
Fractional PLL
(6)
The lower number indicates better jitter performance.
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Transceiver Clocking in Cyclone V Devices

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Transceivers
Transmit PLL
or CDR
Transceiver
Internal Clocks
Channels
Transmitter PLL
CMU PLL
Yes
Yes
Yes
Yes
®
V transceiver clocking architecture. The chapter
Input Reference Clock
FPGA
Fabric
FPGA Fabric-Transceiver
Interface Clocks
CDR
Yes
Yes
Yes
Yes
(6)
Jitter Performance
1
2
3
4
ISO
9001:2008
Registered
2