Altera Cyclone V Device Handbook page 67

4-10
PLL Clock Outputs
Related Information
PLLs and Clocking
Provides more information about HSSI outputs.
LVDS Interface with External PLL Mode
Provides more information about HSSI outputs.
PLL Clock Outputs
The Cyclone V PLL clock outputs can drive both GCLK and RCLK networks.
Clock Input Pin Connections to GCLK and RCLK Networks
Table 4-2: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Cyclone V E, GX, and GT Devices
Clock Resources
GCLK[0,1,2,3,4,5,6,7]
GCLK[8,9,10,11]
GCLK[0,1,2,3,12,13,14,15]
Table 4-3: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Cyclone V SE, SX, and ST Devices
Clock Resources
GCLK[0,1,2,3,4,5,6,7]
GCLK[8,9,10,11]
GCLK[0,1,2,3,12,13,14,15]
Table 4-4: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V E, GX, and GT Devices
A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.
Clock Resources
RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86]
RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87]
RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84]
RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85]
RCLK[46,47,48,49,50,51,70,74,76,80]
RCLK[46,47,48,49,50,51,71,75,77,81]
(2)
For Cyclone V E A2 and A4 devices, and Cyclone V GX C3 device, only
(3)
This applies to all Cyclone V SE, SX, and ST devices except for Cyclone V SE A2 and A4 devices, and
Cyclone V SX C2 and C4 devices.
(4)
This applies to all Cyclone V E, GX, and GT devices except for Cyclone V E A2 and A4 devices, and
Cyclone V GX C3 device.
Altera Corporation
on page 5-12
on page 5-15
CLK (p/n Pins)
CLK[0,1,2,3]
(2)
CLK[4,5,6,7]
CLK[8,9,10,11]
CLK (p/n Pins)
CLK[0,1,2,3]
(3)
CLK[4,5]
CLK[6,7]
CLK (p/n Pins)
CLK[4]
CLK[5]
CLK[6]
Clock Networks and PLLs in Cyclone V Devices
CLK[0]
CLK[1]
CLK[2]
CLK[3]
(4)
(4)
is available.
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CV-52004
2014.01.10