Indirect Write Operation With Dma Enabled; Xip Mode Operations - Altera Cyclone V Device Handbook

12-16

Indirect Write Operation with DMA Enabled

9. Issue a write transaction to the indirect address to write one flash page of data to the SRAM. Repeat
8 if more write transactions are needed to complete the indirect write transfer. The final write may be
less than one page of data.
Related Information
• Indirect Write Operation
• Setting Up the Quad SPI Flash Controller
Indirect Write Operation with DMA Enabled
The following steps describe the general software flow to set up the quad SPI controller for indirect write
operation with the DMA enabled:
1. Perform the steps described in the Setting Up the Quad SPI Flash Controller" section.
2. Set the flash memory start address in the indwrstaddr register.
3. Set the number of bytes to be transferred in the indcnt field of the indwr register.
4. Set the indirect transfer trigger address in the indaddrtrig register.
5. Set the number of bytes for single and burst type DMA transfers in the dmaper register.
6. Optionally set the SRAM watermark level in the indwrwater register to control the rate DMA requests
are issued. The value set must be greater than one flash page. For more information, refer to the Indirect
Write Operation" section.
7. Start the indirect write access by setting the start field of the indirwr register to 1.
8. Either use the indirect complete interrupt to determine when the indirect write operation has completed
or poll the completion status of the indirect write operation through the ind_ops_done_status
field of the indwr register.
Related Information
• Indirect Write Operation
• Setting Up the Quad SPI Flash Controller

XIP Mode Operations

XIP mode is supported in most SPI flash devices. However, flash device manufacturers do not use a consistent
standard approach. Most use signature bits that are sent to the device immediately following the address
bytes. Some devices use signature bits and also require a flash device configuration register write to enable
XIP mode.
Entering XIP Mode
Micron Quad SPI Flash Devices with Support for Basic-XIP
To enter XIP mode in a Micron quad SPI flash device with support for Basic-XIP, perform the following
steps:
1. Save the values in the mode bits, if you intend to restore them upon exit.
2. Disable the direct access controller and indirect access controller to ensure no new read or write accesses
are sent to the flash device.
3. Set the XIP mode bits in the modebit register to 0x80.
Altera Corporation
on page 12-5
on page 12-14
on page 12-5
on page 12-14
cv_54012
2013.12.30
step
Quad SPI Flash Controller
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