Dynamic Oct Control; Ioe Registers - Altera Cyclone V Device Handbook

6-26

Dynamic OCT Control

Figure 6-15: Avoiding Glitch on a Non-Consecutive Read Burst Waveform
This figure shows how to avoid postamble glitches using the HDR block.
Postamble Enable
dqsenable
Dynamic OCT Control
The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip
parallel termination (R
Figure 6-16: Dynamic OCT Control Block for Cyclone V Devices
OCT Control
OCT Control
Related Information
Dynamic OCT in Cyclone V Devices
Provides more information about dynamic OCT control.

IOE Registers

The IOE registers are expanded to allow source-synchronous systems to have faster register-to-FIFO transfers
and resynchronization. All top, bottom, and right IOEs have the same capability.
Altera Corporation
DQS
OCT) on during a read and turn R
T
D Q
DFF
D Q
DFF
OCT Half-Rate Clock
The full-rate write clock comes from the PLL. The DQ write
clock and DQS write clock have a 90° offset between them
on page 5-40
Postamble
OCT off during a write.
T
D
DFF
0
1
D
DFF
Write Clock
External Memory Interfaces in Cyclone V Devices
Postamble glitch
Preamble
Delayed by
1/2T logic
OCT Control Path
Q
1
OCT Enable
0
Q
CV-52006
2014.01.10
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