Altera Cyclone V Device Handbook page 522

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2013.12.30
Figure 4-2: Address Map per Master
The following figure shows the interconnect address map for all MPU and non-MPU masters. The figure is
not to scale.
For the MPU L3 master, either the boot ROM or on-chip RAM maps to address 0x0 and obscures the lowest
64 K of SDRAM. The address space from 0x0001_0000 to 0x0010_0000 is not accessible because the MPU
L2 filter registers only have a granularity of 1 MB. After booting completes, the MPU can change address
filtering to use the lowest 1 MB of SDRAM.
For non-MPU masters, either the on-chip RAM or the SDRAM maps to address 0x0. When mapped to
address 0x0, the on-chip RAM obscures the lowest 64 K of SDRAM for non-MPU masters.
Interconnect
Send Feedback
0xFFFF_FFFF
On-Chip RAM
0xFFFF_0000
SCU & L2 Registers
0xFFFE_C000
Boot ROM
0xFFFD_0000
Peripherals &
0xFF40_0000
Lightweight FPGA Slaves
0xFF20_0000
0xFF00_0000
0xFC00_0000
FPGA Slaves
0xC000_0000
0x8000_0000
SDRAM
0x0010_0000
0x0001_0000
Boot ROM or On-Chip RAM
0x0000_0000
Notes:
(1) The SCU and L2 cache registers are located in the MPU subsystem and are not accessible
from the L3 interconnect.
(2) This address range is not always accessible.
(3) The MPU subsystem has one master that connects to the interconnect and another
master that connects directly to the SDRAM controller subsystem. The address filter
registers in the MPU L2 control which MPU addresses are sent to each master. This figure
assumes the filter registers contain their reset values.
(4) This address range is configurable.
(5) This address range is not accessible from the master peripheral interfaces.
(6) This address range is not accessible from the DAP interface.
(1)
L3 GPV
(2)
Lightweight FPGA Slaves
DAP
STM
(2)
(3)
(4)
On-Chip RAM or SDRAM
MPU
Address Remapping
On-Chip RAM
Peripherals &
(5)
L3 GPV
(2)
(5)
DAP
(5), (6)
STM
(2)
FPGA Slaves
ACP
SDRAM
(4)
non-MPU
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