Altera Cyclone V Device Handbook page 892

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2013.12.30
Figure 17-13: Receive Descriptor Fields Format
TDES0
TDES1
T D E 2 S
T D E 3 S
T D E 4 S
T D E 5 S
T D E 6 S
T D E 7 S
Receive Descriptor Field 0 (RDES0)
Table 17-14: Receive Descriptor Field 0 (RDES0)
Bit
31
30
Ethernet Media Access Controller
Send Feedback
31 30 29 28 27 26 25 24 23
O
W
N
C
T RES
Buffer 2 Byte Count [28:16]
R [30:29]
L
u B
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the EMAC. When
this bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears
this bit either when it completes the frame reception or when the buffers that are associated
with this descriptor are full.
AFM: Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the MAC.
22 21 20 19 18 17 16 15 14
Status [30:0]
Ctrl
[15:14]
u B e f f 1 r d A r d s e [ s 1 3
e f f 2 r d A r d s e [ s 1 3 ] 0 : r o e N t x e D c s
x E e t d n d e s a t u t [ s 1 3
e R e s v r d e
T a r s n i m T t m i s e a t m p o L [ w
T a r s n i m T t m i s e a t m p H g i
Description
Receive Descriptor Field 0 (RDES0)
13 12 11 10 9 8 7 6 5
R
E Buffer 1 Byte Count [12:0]
S
] 0 :
p i r r o t d A r d s e [ s 1 3 ] 0 :
] 0 :
1 3 ] 0 :
[ h 1 3 ] 0 :
17-43
4 3 2 1 0
†
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