Altera Cyclone V Device Handbook page 812

16-16
Abort Sources
Abort Sources
The DMAC indicates a precise abort under any of the following conditions:
• A DMA channel thread in the Non-secure state attempts to program its CCRn register and generate a
secure AXI transaction.
• A DMA channel thread in the Non-secure state executes DMAWFE or DMASEV for an event that is set as
secure. The boot_irq_ns memory-mapped control signals initialize the security state for an event.
Note: For each event, the INTEN register controls if the DMAC generates an event or signals an interrupt.
• A DMA channel thread attempts to execute DMAST but the DMAC calculates that when it eventually
performs the store, the MFIFO buffer contains insufficient data to enable it to complete the store.
• A DMA channel thread in the Non-secure state executes DMAWFP, DMALDP, DMASTP, or DMAFLUSHP
for a peripheral request interface that is set as secure. The boot_periph_ns memory-mapped control
signals initialize the security state for a peripheral request interface.
• A DMA manager thread in the Non-secure state executes DMAGO to attempt to start a secure DMA
channel thread.
• The DMAC receives an ERROR response on the AXI master interface when it performs an instruction
fetch.
• A thread executes an undefined instruction.
• A thread executes an instruction with an operand that is invalid for the configuration of the DMAC.
Note: When the DMAC signals a precise abort, the instruction that triggers the abort is not executed.
Instead, the DMAC executes a DMANOP.
The DMAC signals an imprecise abort under the following conditions:
• The DMAC receives an ERROR response on the AXI master interface when it performs a data load.
• The DMAC receives an ERROR response on the AXI master interface when it performs a data store.
• A DMA channel thread executes DMALD or DMAST, and the MFIFO buffer is too small to hold the
required amount of data.
• A DMA channel thread executes DMAST but the thread has not executed sufficient DMALD instructions.
• A DMA channel thread locks up because of resource starvation, and this causes the internal watchdog
timer to time out.
Watchdog Abort
The DMAC can lock up if one or more DMA channel programs are running and the MFIFO buffer is too
small to satisfy the storage requirements of the DMA programs.
The DMAC contains logic to prevent it from remaining in a state where it is unable to complete a DMA
transfer.
The DMAC detects a lock up when all of the following conditions occur:
• Load queue is empty.
• Store queue is empty.
• All of the running channels are prevented from executing a DMALD instruction either because the MFIFO
buffer does not have sufficient free space or another channel owns the load-lock.
Altera Corporation
cv_54016
2013.12.30
DMA Controller
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