Altera Cyclone V Device Handbook page 191

CV-52006
2014.01.10
Figure 6-5: DQS Pins and DLLs in Cyclone V SE (A2, A4, A5, and A6) Devices
External Memory Interfaces in Cyclone V Devices
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DQS
Pin
DLL
Reference
Clock
Δt
DLL to IOE
to IOE
to to
DLL
IOE IOE
Δt Δt
DLL
Reference
Clock
DQS DQS
Pin Pin
DQS
Pin
Δt
HPS I/O
HPS
to IOE
PLL
HPS Block
to IOE
to to
IOE IOE
Δt Δt
DQS Logic
Blocks
DQS DQS
Pin Pin
DQS Phase-Shift Circuitry
DLL
DQS Logic
Blocks
DQS
Δt
Pin
DQS
Δt
Pin
to DQS
Δt
IOE Pin
to
IOE
DQS
Δt
Pin
DQS Logic
Blocks
DLL
DLL
Reference
Clock
6-17
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