Altera Cyclone V Device Handbook page 884

cv_54017
2013.12.30
a group are cleared, the corresponding summary bit is cleared. When both the summary bits are cleared,
the sbd_intr_o interrupt signal is de-asserted. If the MAC is the cause for assertion of the interrupt, then
any of the GLI, GMI, GPI, TTI, or GLPII bits of Register 5 (Status Register) are set high.
Figure 17-10: sbd_intr_o Generation
Note: The Register 5 (Status Register) is the interrupt status register. The interrupt pin (sbd_intr_o) is
asserted because of any event in this status register only if the corresponding interrupt enable bit is
set in Register 7 (Interrupt Enable Register).
Interrupts are not queued and if the interrupt event occurs before the driver has responded to it, no additional
interrupts are generated. For example, Bit 6 (Receive Interrupt) of Register 5 (Status Register) indicates that
one or more frames were transferred to the Host buffer. The driver must scan all descriptors, from the last
recorded position to the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan the Register 5
(Status Register) for the cause of the interrupt. The interrupt is not generated again unless a new interrupting
event occurs, after the driver has cleared the appropriate bit in Register 5 (Status Register). For example, the
controller generates a Bit 6 (Receive Interrupt) of Register 5 (Status Register) and the driver begins reading
Register 5 (Status Register). Next, Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) occurs.
The driver clears the receive interrupt. Even then, the sbd_intr_o signal is not de-asserted, because of the
active or pending Receive Buffer Unavailable interrupt.
Bits 7:0 (Interrupt Timer) of Register 9 (Receive Interrupt Watchdog Timer Register) is given for flexible
control of receive Interrupt. When this Interrupt timer is programmed with a non-zero value, it gets activated
as soon as the RX DMA completes a transfer of a received frame to system memory without asserting the
receive Interrupt because it is not enabled in the corresponding Receive Descriptor (RDES1[31]. When this
timer runs out as per the programmed value, RI bit is set and the interrupt is asserted if the corresponding
RI is enabled in Register 7 (Interrupt Enable Register). This timer gets disabled before it runs out, when a
frame is transferred to memory and the RI is set because it is enabled for that descriptor.
Related Information
Receive Descriptor
Error Response to DMA
For any data transfer initiated by a DMA channel, if the slave replies with an error response, that DMA stops
all operations and updates the error bits and the Fatal Bus Error bit in the Register 5 (Status Register). The
DMA controller can resume operation only after soft resetting or hard resetting the EMAC and reinitializing
the DMA.
(43)
Signals NIS and AIS are registered.
Ethernet Media Access Controller
Send Feedback
(43)
TI
NIS
TIE
NIE
ERI
ERE
TPS
AIS
TSE
AIE
FBI
FBE
on page 17-42
Error Response to DMA
TTI
GPI
GMI
GLI
GLPII/GTMSI
sbd_intr_o
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17-35
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