Architecture Overview - Altera Cyclone V Device Handbook

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Architecture Overview

Architecture Overview
Figure 1-1: Basic Layout of Transceivers in a Cyclone V Device
This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different
floor plan than the one shown here.
The embedded high-speed clock networks in Cyclone V devices provide dedicated clocking connectivity for
the transceivers. You can also use the fractional phase-locked loop (fPLL) between the PMA and PCS to
clock the transceivers.
The embedded PCIe hard intellectual property (IP) of Cyclone V devices implements the following PCIe
protocol stacks:
• Physical interface/media access control (PHY/MAC) layer
• Data link layer
• Transaction layer
The embedded hard IP saves significant FPGA resources, reduces design risks, and reduces the time required
to achieve timing closure. The hard IP complies with the PCIe Base Specification 2.0 for Gen1 and Gen2
signaling data rates.
Related Information
• Transceiver Clocking in Cyclone V Devices
Altera Corporation
I/O, LVDS, and Memory Interface
Hard Memory Controller
Hard Memory Controller
I/O, LVDS, and Memory Interface
Transceiver Hard
PMA PCS
Transceiver Hard
PMA PCS
Transceiver Hard
PMA PCS
Transceiver Hard
PMA PCS
Transceiver
Individual Channels
Distributed Memory
Core Logic Fabric and MLABs
M10K Internal Memory Blocks
Variable-Precision DSP Blocks
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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