Fpga Interface - Altera Cyclone V Device Handbook

7-12

FPGA Interface

Table 7-4: STM Master ID Calculation
Master ID Bits
Master
AWADDRS[29:24]
ID[5:0]
Master
AWPROT[1]
ID[6]
In addition to access through STM channels, the higher-order 28 (31:4) of the 32 event signals are attached
to the FPGA through the FPGA-CTI. These event signals allow the FPGA fabric to send additional messages
using the STM.
Related Information
Info center
For more information, refer to the System Trace Macrocell in the Programmers' Model Architecture
Specification.
FPGA Interface
The following components connect to the FPGA fabric. This section lists the signals from debug system to
the FPGA.
DAP
The DAP uses the system APB port to connect to the FPGA.
Table 7-5: DAP
The following table shows the signal description between DAP and FPGA.
Segment
h2f_dbg_apb_PADDR[18]
h2f_dbg_apb_PADDR31
h2f_dbg_apb_PENABLE
h2f_dbg_apb_PRDATA[32]
h2f_dbg_apb_PREADY
h2f_dbg_apb_PSEL
h2f_dbg_apb_PSLVERR
h2f_dbg_apb_PSLVERR
h2f_dbg_apb_PWRITE
STM
The STM has 28 event pins, f2h_stm_hw_events[28], for FPGA to trigger events to STM.
Altera Corporation
AXI Signal Bits
Address bus to system APB port
Address bus to system APB port
Enable signal from system APB port
32-bit system APB port read data bus
Ready signal to system APB port
Select signal from system APB port
Error signal to system APB port
32-bit system APB port write data bus
Select whether read or write to system APB port
• 0 - System APB port read from DAP
• 1 - System APB Port write to DAP
The lowest two bits are sufficient to determine which
master, but CoreSight uses a seven-bit master ID.
0 indicates secure; 1 indicates nonsecure.
Description
Notes
CoreSight Debug and Trace
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2013.12.30