Transmit And Receive Data Fifo Buffers; Ieee 1588-2002 Timestamps - Altera Cyclone V Device Handbook

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2013.12.30

Transmit and Receive Data FIFO Buffers

Each EMAC component has associated transmit and receive data FIFO buffer instances. Both FIFO buffer
instances are 1024 x 42 bits. The FIFO buffer word consists of:
• Data: 32 bits
• Sideband:
• • Byte enables (BE): 2 bits
• End of frame (EOF): 1 bit
• Error correction code (ECC): 7 bits
The data and sideband are protected by the 7-bit single error correct, double error detect (SEC-DED) code
word. These FIFO buffer RAMs also contain ECC enable, error injection and status pins. The enable and
error injection pins are inputs driven by the system manager and the status pins are outputs driven to the
MPU subsystem.

IEEE 1588-2002 Timestamps

The IEEE 1588-2002 standard defines the Precision Time Protocol (PTP) which enables precise synchroniza-
tion of clocks in a distributed network of devices. The PTP applies to systems communicating by local area
networks supporting multicast messaging. This protocol enables heterogeneous systems that include clocks
of varying inherent precision, resolution, and stability to synchronize. It is frequently used in automation
systems where a collection of communicating machines such as robots must be synchronized and hence
operate over a common time base.
The PTP is transported over UDP/IP. The system or network is classified into Master and Slave nodes for
distributing the timing and clock information.
The following figure shows the process that PTP uses for synchronizing a slave node to a master node by
exchanging PTP messages.
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Transmit and Receive Data FIFO Buffers
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