Altera Cyclone V Device Handbook page 189

CV-52006
2014.01.10
Figure 6-3: DQS Pins and DLLs in Cyclone V GX (C3) Devices
External Memory Interfaces in Cyclone V Devices
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DQS DQS
Pin Pin
DLL
Reference
Clock
Δt Δt
DLL to to
IOE IOE
to IOE to IOE
Δt Δt
DQS DQS
Pin Pin
DQS DQS
Pin Pin
DLL
DQS Logic
Reference
Blocks
Clock
Δt Δt
to to DLL
IOE IOE
to
IOE
to
IOE
to
IOE
to
IOE
DLL
to IOE to IOE
Δt Δt
DLL
Reference
Clock
DQS DQS
Pin Pin
DQS Phase-Shift Circuitry
DQS Logic
Blocks
DQS
Δt
Pin
DQS
Δt
Pin
DQS
Δt
Pin
DQS
Δt
Pin
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