Altera Cyclone V Device Handbook page 551

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Jazelle DBX extension per Cortex-A9 processor

PTM interface per Cortex-A9 processor

Support for parity error detection

Master ports

Accelerator Coherency Port

Related Information

ARM Infocenter (www.infocenter.arm.com)

Cortex-A9 Processor

Each Cortex-A9 processor includes the following hardware blocks:

v3 double-precision floating point unit for media and signal processing acceleration

• Single- and double-precision IEEE-754 floating point math support

• Integer and polynomial math support

• Level 1 (L1) cache with parity checking

• 32 KB four-way set-associative instruction cache

• 32 KB four-way set-associative data cache

Each Cortex-A9 processor supports the following features:

• Dual-issue superscalar pipeline with advanced branch prediction

• Out-of-order (OoO) dispatch and speculative instruction execution

• 2.5 million instructions per second (MIPS) per MHz, based on the Dhrystone 2.1 benchmark

• 128-entry translation lookaside buffer (TLB)

• TrustZone security extensions

• Configurable data endianness

For a description of the parity error scheme and parity error signals, refer to the Cortex-A9 Technical Reference

Manual, available on the ARM website (infocenter.arm.com).

Cortex-A9 Microprocessor Unit Subsystem

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single instruction, multiple data (SIMD) coprocessor with vector floating-point (VFP)

Program Trace Macrocell (PTM) supporting instruction trace

Cortex-A9 Processor

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