Altera Cyclone V Device Handbook page 594

cv_54007
2013.12.30
FPGA-CTI
The FPGA-CTI allows FPGA to send and receive triggers from debug system.
Table 7-6: FPGA-CTI
The following table shows the signal description between FPGA-CTI and FPGA.
h2f_cti_trig_in[8]
h2f_cti_trig_in_ack[8]
h2f_cti_trig_out[8]
h2f_cti_trig_out_ack[8]
h2f_cti_clk
h2f_cti_fpga_clk_en
h2f_cti_asicctl[8]
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CTI-NoC
CTI-NoC has all of its triggers available to the NoC interconnect.
TPIU
Signal descriptions between TPIU and FPGA.
Table 7-7: TPIU
h2f_tpiu_clk_ctl
h2f_tpiu_data[32]
h2f_tpiu_clock_in
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Signal
Signal
Trigger input from FPGA
ACK signal to FPGA
Trigger output to FGPA
ACK signal from FPGA
Clock input from FPGA
Clock enable driven by FPGA
Signal from FPGA
Selects whether trace data is captured using the
internal TPIU clock or an external clock provided as
an input to the TPIU from the FPGA.
0 - use h2f_tpiu_clock_in
1 - use internal clock
Note: When the FPGA is powered down or not
configured the TPIU uses the internal clock.
32 bit trace data bus to the FPGA. Trace data changes
on both edges of h2f_tpiu_clock.
Note: When the FPGA is powered down or not
configured, the TPIU sends the lower 8-bits trace data
to I/Os.
Clock from the FPGA used to capture trace data.
FPGA-CTI
Description
Description
7-13
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