Altera Cyclone V Device Handbook page 696

11-18
CCS Detection and Interrupt to Host Processor
CCS Detection and Interrupt to Host Processor
If the ccs_expected bit in the cmd register is set to 1, the CCS from the CE-ATA card device is indicated
by setting the data transfer over bit (dto) in the rintsts register. The controller generates a DTO interrupt
if this interrupt is not masked.
For the RW_MULTIPLE_BLOCK commands, if the CE-ATA card device interrupts are disabled (the nIEN
bit is set to 1 in the ATA control register)
register there are no CCSs from the card. When the data transfer is over that is, when the requested
number of bytes are transferred the dto bit in the rintsts register is set to 1.
CCS Timeout
If the command expects a CCS from the card device (the ccs_expected bit is set to 1 in the cmd register),
the command state machine waits for the CCS and remains in the wait CCS state. If the CE-ATA card fails
to send out the CCS, the host software must implement a timeout mechanism to free the command and data
path. The controller does not implement a hardware timer; it is the responsibility of the host software to
maintain a software timer.
In the event of a CCS timeout, the host must issue a CCSD command by setting the send_ccsd bit in the
ctrl register. The controller command path state machine sends the CCSD command to the CE-ATA card
device and exits to an idle state. After sending the CCSD command, the host must also send an SD/SDIO
STOP_TRANSMISSION command to the CE-ATA card to abort the outstanding ATA command.
Send CCSD Command
If the send_ccsd bit in the ctrl register is set to 1, the controller sends a CCSD pattern on the CMD
line. The host can send the CCSD command while waiting for the CCS or after a CCS timeout happens.
After sending the CCSD pattern, the controller sets the cmd bit in the rintsts register and also generates
an interrupt to the host if the Command Done interrupt is not masked.
Note: Within the CIU block, if the send_ccsd bit in the ctrl register is set to 1 on the same clock cycle
as CCS is sampled, the CIU block does not send a CCSD pattern on the CMD line. In this case, the
dto and cmd bits in the rintsts register are set to 1.
Note: Due to asynchronous boundaries, the CCS might have already happened and the send_ccsd bit
is set to 1. In this case, the CCSD command does not go to the CE-ATA card device and the
send_ccsd bit is not set to 0. The host must reset the send_ccsd bit to 0 before the next
command is issued.
If the send auto stop CCSD (send_auto_stop_ccsd) bit in the ctrl register is set to 1, the controller
sends an internally generated STOP_TRANSMISSION command (CMD12) after sending the CCSD pattern.
The controller sets the acd bit in the rintsts register.
I/O transmission delay (N
The host software maintains the timeout mechanism for handling the I/O transmission delay (N
time-outs while reading from the CE-ATA card device. The controller neither maintains any timeout
mechanism nor indicates that N
I/O transmission delay is applicable for read transfers using the RW_REG and RW_BLK commands; the
RW_REG and RW_BLK commands used in this document refer to the RW_MULTIPLE_REGISTER and
RW_MULTIPLE_BLOCK MMC commands defined by the CE-ATA specification.
Altera Corporation
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that is, the ccs_expected bit is set to 0 in the cmd
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Timeout)
ACIO
cycles are elapsed while waiting for the start bit of a data token. The
ACIO
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cv_54011
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cycles)
ACIO
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SD/MMC Controller
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