Transmitter Pll - Altera Cyclone V Device Handbook

1-20

Transmitter PLL

The deterministic latency state machine in the word aligner from the PCS automatically controls the clock-
slip operation. After completing the clock-slip process, the deserialized data is word-aligned into the receiver
PCS.
Transmitter PLL
In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and
fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR)
PLL.
Note: Cyclone V transceiver channels support full-duplex operation. The CMU PLL is sourced from the
channel PLL of channels 1 or 4.
Table 1-8: Transmitter PLL Capability and Availability
Transmitter PLL
CMU PLL
fPLL
Related Information
Transceiver Clocking in Cyclone V Devices
Channel PLL Architecture
In LTR mode, the channel PLL tracks the input reference clock. The PFD compares the phase and frequency
of the voltage controlled oscillator (VCO) output and the input reference clock. The resulting PFD output
controls the VCO output frequency to half the data rate with the appropriate counter (M or L) value given
an input reference clock frequency. The lock detect determines whether the PLL has achieved lock to the
phase and frequency of the input reference clock.
In LTD mode, the channel PLL tracks the incoming serial data. The phase detector compares the phase of
the VCO output and the incoming serial data. The resulting phase detector output controls the VCO output
to continuously match the phase of the incoming serial data.
The channel PLL supports operation in either LTR or LTD mode.
Note: Use the LTR/LTD controller only when the channel PLL is configured as a CDR PLL.
Table 1-9: Channel PLL Counters
®
The Quartus II software automatically selects the appropriate counter values for each transceiver configuration.
Counter
N
M
L (PFD)
Altera Corporation
Serial Data Range
0.611 Gbps to 6.144 Gbps
0.611 Gbps to 3.125 Gbps
Pre-scale counter to divide the input reference clock
frequency to the PFD by the N factor
Feedback loop counter to multiply the VCO frequency above
the input reference frequency to the PFD by the M factor
VCO post-scale counter to divide the VCO output frequency
by the L factor in the LTR loop
Every channel when not used as receiver CDR
Two per transceiver bank
Description
Availability
Values
1, 2, 4, 8
1, 4, 5, 8, 10, 12, 16, 20, 25
1, 2, 4, 8
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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