Altera Cyclone V Device Handbook page 449

TOC-10
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
Functional Description of the DMA Controller....................................................................................16-3
DMA Controller Programming Model................................................................................................16-26
DMA Controller Registers......................................................................................................................16-52
Document Revision History...................................................................................................................16-53
Ethernet Media Access Controller....................................................................17-1
Features of the Ethernet MAC.................................................................................................................17-1
EMAC Block Diagram and System Integration....................................................................................17-3
Functional Description of the EMAC.....................................................................................................17-9
Altera Corporation
Operating States.............................................................................................................................16-4
Error Checking and Correction...................................................................................................16-7
Initializing the DMAC..................................................................................................................16-7
Using the Slave Interfaces.............................................................................................................16-9
Peripheral Request Interface......................................................................................................16-10
Using Events and Interrupts......................................................................................................16-14
Aborts............................................................................................................................................16-15
Security Usage..............................................................................................................................16-18
Constraints and Limitations of Use..........................................................................................16-22
Programming Restrictions.........................................................................................................16-23
Instruction Syntax Conventions................................................................................................16-26
Instruction Set Summary............................................................................................................16-27
Instructions...................................................................................................................................16-28
Assembler Directives...................................................................................................................16-42
MFIFO Buffer Usage Overview.................................................................................................16-44
Address Map and Register Definitions.....................................................................................16-53
MAC................................................................................................................................................17-1
PHY Interface.................................................................................................................................17-2
DMA Interface...............................................................................................................................17-2
Management Interface..................................................................................................................17-2
Acceleration....................................................................................................................................17-2
Other Features................................................................................................................................17-2
EMAC to RGMII Interface...........................................................................................................17-3
EMAC to FPGA PHY Interface...................................................................................................17-5
PHY Management Interface.........................................................................................................17-8
IEEE 1588........................................................................................................................................17-8
Host Interfaces...............................................................................................................................17-9
External PHY................................................................................................................................17-10
Transmit and Receive Data FIFO Buffers................................................................................17-11