External Phy - Altera Cyclone V Device Handbook

17-10
DMA Master
DMA Master
The DMA interface is provided by a master interface. Two types of data are transferred on the interface:
data descriptors and actual data packets. The interface is very efficient in transferring full duplex Ethernet
packet traffic. Read and write data transfers from different DMA channels can be performed simultaneously
on this port. The only exceptions to this are transmit descriptor reads and write-backs which cannot happen
simultaneously.
DMA transfers are split into a software configurable number of burst transactions on the interface. The
AXI_Bus_Mode register in the dmagrp group is used to configure bursting behavior.
The interface assigns a unique ID for each DMA channel and also for each read DMA or write DMA request
in a channel. Data transfers with distinct IDs can be reordered and interleaved.
Write data transfers are generally performed as posted writes with OK responses returned as soon as the
interconnect has accepted the last beat of a data burst. Descriptors (status or timestamp) however are always
transferred as non-posted writes in order to prevent race conditions with the transfer complete interrupt
logic.
The slave may issue an error response. When that happens, the EMAC disables the DMA channel which
generated the original request and asserts an interrupt signal. The host needs to reset the EMAC with a hard
or soft reset to restart the DMA to recover from this condition.
The EMAC supports up to 16 outstanding transactions on the interface. Buffering outstanding transactions
smooths out back pressure behavior. This is important when resource contention bottlenecks arise under
high system load conditions.
Cache Control Interface
The system manager provides the values for the master cache outputs through this interface. These inputs
are used as the outputs to the L3 interconnect extending the capabilities of this block with respect to the
cacheable characteristics of master transfers.
To configure EMAC DMA controller to perform cacheable accesses, configure the cache bits in the system
manager. Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
System Manager

External PHY

The following PHY interfaces are supported for the HPS:
• RGMII for 10/100/1000
The EMAC also has a control interface used for configuration and status monitoring of the PHY. In this
case, the PHY is the slave device. There are two choices of control interface:
• MDIO
2
• I C interface
The MDIO interface is built into the EMAC while the I
on the HPS. The interfaces are multiplexed externally to the EMAC.
Altera Corporation
on page 14-1
2
C interface uses separate I
Ethernet Media Access Controller
cv_54017
2013.12.30
2
C peripherals residing
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